Semiconductor memory device capable of detecting bridge defects and bridge defect detecting method performed in the semiconductor memory device

Abstract

A bridge defect detecting method performed in a semiconductor memory device that includes a plurality of memory cells arranged at intersections between a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers connected to the bit lines, includes the operations of: enabling a first sense amplifier and a second sense amplifier; keeping the first sense amplifier in an enabled state and disabling the second sense amplifier; enabling the second sense amplifier, and detecting a bridge defect between the first memory cell and the second memory cell by reading data from a first memory cell of a first bit line connected to the first sense amplifier and a second memory cell of a second bit line connected to the second sense amplifier.