The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7692943 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 06, 2010

Filed:

Dec. 10, 2007
Applicants:

Kenichi Osada, Tokyo, JP;

Takayuki Kawahara, Higashiyamato, JP;

Ken Yamaguchi, Fuchu, JP;

Yoshikazu Saito, Hamura, JP;

Naoki Kitai, Fussa, JP;

Inventors:

Kenichi Osada, Tokyo, JP;

Takayuki Kawahara, Higashiyamato, JP;

Ken Yamaguchi, Fuchu, JP;

Yoshikazu Saito, Hamura, JP;

Naoki Kitai, Fussa, JP;

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.


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Osada, Kenichi. (2010). Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to n wells and p wells (U.S. Patent No. 7692943). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7692943

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