Output buffer circuit and differential output buffer circuit, and transmission method

Abstract

In an output buffer circuit including Inverterto Inverter, Delay Circuitto Delay Circuitfor delaying an input signal for a specific time, Bufferto Buffer, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuitto Selector circuitare situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.