The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2010
Filed:
Feb. 27, 2006
C. Grant Willson, Austin, TX (US);
Frank Palmieri, Austin, TX (US);
Yukio Nishimura, Yokkaichi, JP;
Stephen C. Johnson, Austin, TX (US);
Michael D. Stewart, Austin, TX (US);
C. Grant Willson, Austin, TX (US);
Frank Palmieri, Austin, TX (US);
Yukio Nishimura, Yokkaichi, JP;
Stephen C. Johnson, Austin, TX (US);
Michael D. Stewart, Austin, TX (US);
Board of Regents, The University of Texas System, Austin, TX (US);
Abstract
In some embodiments, the present invention is directed to methods that involve the combination of step-and-flash imprint lithography (SFIL) with a multi-tier template to simultaneously pattern multiple levels of, for example, an integrated circuit device. In such embodiments, the imprinted material generally does not serve or act as a simple etch mask or photoresist, but rather serves as the insulation between levels and lines, i.e., as a functional dielectric material. After imprinting and a multiple step curing process, the imprinted pattern is filled with metal, as in dual damascene processing. Typically, the two printed levels will comprise a 'via level,' which is used to make electrical contact with the previously patterned under-level, and a 'wiring level.' The present invention provides for the direct patterning of functional materials, which represents a significant departure from the traditional approach to microelectronics manufacturing.