The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

Dec. 19, 2007
Applicants:

Payman Zarkesh-ha, Albuquerque, NM (US);

Christopher L. Hamlin, Los Gatos, CA (US);

Ashok K. Kapoor, Palo Alto, CA (US);

James S. Koford, Monterey, CA (US);

Madhukar B. Vora, Los Gatos, CA (US);

Inventors:

Payman Zarkesh-Ha, Albuquerque, NM (US);

Christopher L. Hamlin, Los Gatos, CA (US);

Ashok K. Kapoor, Palo Alto, CA (US);

James S. Koford, Monterey, CA (US);

Madhukar B. Vora, Los Gatos, CA (US);

Assignee:

SuVolta, Inc., Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.


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