The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2010
Filed:
Mar. 24, 2004
Karl M. J. Lofgren, Newport Beach, CA (US);
Jeffrey Donald Stai, Placentia, CA (US);
Anil Gupta, Irvine, CA (US);
Robert D. Norman, San Jose, CA (US);
Sanjay Mehrotra, Milpitas, CA (US);
Karl M. J. Lofgren, Newport Beach, CA (US);
Jeffrey Donald Stai, Placentia, CA (US);
Anil Gupta, Irvine, CA (US);
Robert D. Norman, San Jose, CA (US);
Sanjay Mehrotra, Milpitas, CA (US);
SanDisk Corporation, Milpitas, CA (US);
Abstract
A memory system includes an array of solidstate memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.