The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

Nov. 14, 2007
Applicants:

Markus Brunnbauer, Lappersdorf, DE;

Jens Pohl, Bernhardswald, DE;

Klaus Pressel, Regensburg, DE;

Thorsten Meyer, Regensburg, DE;

Recai Sezi, Roettenbach, DE;

Stephan Bradl, Regensburg, DE;

Ralf Plieninger, Poing, DE;

Inventors:

Markus Brunnbauer, Lappersdorf, DE;

Jens Pohl, Bernhardswald, DE;

Klaus Pressel, Regensburg, DE;

Thorsten Meyer, Regensburg, DE;

Recai Sezi, Roettenbach, DE;

Stephan Bradl, Regensburg, DE;

Ralf Plieninger, Poing, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/043 (2006.01); H01L 23/10 (2006.01); H01L 23/34 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.


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