The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Apr. 11, 2007
Evanthia Papadopoulou, Baldwin Place, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Mervyn Y. Tan, Hopewell Junction, NY (US);
Louise H. Trevillyan, Katonah, NY (US);
Hua Xiang, Ossining, NY (US);
Evanthia Papadopoulou, Baldwin Place, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Mervyn Y. Tan, Hopewell Junction, NY (US);
Louise H. Trevillyan, Katonah, NY (US);
Hua Xiang, Ossining, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.