The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Feb. 09, 2007
Gary D. Grise, Colchester, VT (US);
Vikram Iyengar, South Burlington, VT (US);
Mark R. Taylor, Essex Junction, VT (US);
Gary D. Grise, Colchester, VT (US);
Vikram Iyengar, South Burlington, VT (US);
Mark R. Taylor, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for testing logic devices configured across asynchronous clock domains includes deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto. The deactivation of a local clock signal for each of the plurality of latches is implemented in a manner so as to permit data capture within the first plurality of latches, and wherein the deactivation of a local clock signal for each of the plurality of latches is further implemented in a manner so as to permit at-speed data launch therefrom to downstream latches with respect thereto during at-speed testing.