The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Feb. 01, 2007
Robert Rozbicki, San Francisco, CA (US);
Bart Van Schravendijk, Sunnyvale, CA (US);
Tom Mountsier, San Jose, CA (US);
Wen Wu, San Jose, CA (US);
Robert Rozbicki, San Francisco, CA (US);
Bart van Schravendijk, Sunnyvale, CA (US);
Tom Mountsier, San Jose, CA (US);
Wen Wu, San Jose, CA (US);
Novellus Systems, Inc., San Jose, CA (US);
Abstract
Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.