The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2010

Filed:

Apr. 12, 2006
Applicants:

Hiromitsu Mashita, Sagamihara, JP;

Tadahito Fujisawa, Yokkaichi, JP;

Minoru Inomoto, Suzuka, JP;

Koji Hashimoto, Yokohama, JP;

Yasunobu Kai, Yokohama, JP;

Inventors:

Hiromitsu Mashita, Sagamihara, JP;

Tadahito Fujisawa, Yokkaichi, JP;

Minoru Inomoto, Suzuka, JP;

Koji Hashimoto, Yokohama, JP;

Yasunobu Kai, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.


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