The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Mar. 31, 2005
Michael G. Ludwig, Sunnyvale, CA (US);
Jayant B. Kolhe, Milpitas, CA (US);
Robert Steven Glanville, Cupertino, CA (US);
Geoffrey C. Berry, San Francisco, CA (US);
Boris Beylin, Palo Alto, CA (US);
Michael T. Bunnell, Pleasanton, CA (US);
Michael G. Ludwig, Sunnyvale, CA (US);
Jayant B. Kolhe, Milpitas, CA (US);
Robert Steven Glanville, Cupertino, CA (US);
Geoffrey C. Berry, San Francisco, CA (US);
Boris Beylin, Palo Alto, CA (US);
Michael T. Bunnell, Pleasanton, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for optimizing register allocation during scheduling and execution of program code in a hardware environment. The program code can be compiled to optimize execution given predetermined hardware constraints. The hardware constraints can include the number of register read and write operations that can be performed in a given processor pass. The optimizer can initially schedule the program using virtual registers and a goal of minimizing the amount of active registers at any time. The optimizer reschedules the program to assign the virtual registers to actual physical registers in a manner that minimizes the number of processor passes used to execute the program.