Scheme for screening weak memory cell

Abstract

A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC. The applied leakage stress is adjusted to establish a desired pass/fail threshold and to detect other process variations or defects so that the sense amplifier can be applied to detect the voltage differential during a read operation. The applied leakage stress can also be applied to write driver circuitry such that a write driver along with the applied stress provide enough voltage level to screen difficult-to-write cell from a easy-to-write cell during a write operation. The plurality of stress inducing signals are controlled such that the appropriate leakage stress may be applied to force a leakage to Vdd or Vss associated with the cell through the complementary data lines.