The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Oct. 31, 2007
Jae-woong Hyun, Uijeongbu-si, KR;
Kyu-charn Park, Pyeongtaek-si, KR;
Yoon-dong Park, Yongin-si, KR;
Won-joo Kim, Hwaseong-si, KR;
Young-gu Jin, Hwaseong-si, KR;
Suk-pil Kim, Yongin-si, KR;
Kyoung-iae Cho, Yongin-si, KR;
Jung-hoon Lee, Seoul, KR;
Seung-hwan Song, Incheon, KR;
Jae-woong Hyun, Uijeongbu-si, KR;
Kyu-charn Park, Pyeongtaek-si, KR;
Yoon-dong Park, Yongin-si, KR;
Won-joo Kim, Hwaseong-si, KR;
Young-gu Jin, Hwaseong-si, KR;
Suk-pil Kim, Yongin-si, KR;
Kyoung-Iae Cho, Yongin-si, KR;
Jung-hoon Lee, Seoul, KR;
Seung-hwan Song, Incheon, KR;
Samsung Elecronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor layer, and the plurality of upper control gate electrodes and the plurality of lower control gate electrodes are disposed alternately. A plurality of upper charge storage layers are interposed between the semiconductor layer and the upper control gate electrodes. A plurality of lower charge storage layers are interposed between the semiconductor layer and the lower control gate electrodes.