The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2010

Filed:

Aug. 05, 2005
Applicants:

Yew Fatt Kok, Penang, MY;

Chooi Pei Lim, Penang, MY;

Kok Heng Choe, Penang, MY;

Inventors:

Yew Fatt Kok, Penang, MY;

Chooi Pei Lim, Penang, MY;

Kok Heng Choe, Penang, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques are provided for controlling an on-chip termination (OCT) in an output driver. The OCT control circuit calibrates the effective resistance of transistors in the output driver to match an external resistor using a feedback loop. The feedback loop monitors the output voltage and generates an analog calibration signal that varies the output impedance of a selected group of the output transistors that are enabled to drive the output terminal. Digital signals under the control of the user select the number of output transistors to be enabled based on the output driver requirements of the circuit. The analog calibration signal varies the signal level driving the selected output transistors to modify the effective output impedance of the circuit for better termination matching.


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