The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Nov. 07, 2007
Yakov Roizin, Migdal Haemek, IL;
Victor Kairys, Migdal Haemek, IL;
Erez Sarig, Migdal Haemek, IL;
David Zfira, Migdal Haemek, IL;
Yakov Roizin, Migdal Haemek, IL;
Victor Kairys, Migdal Haemek, IL;
Erez Sarig, Migdal Haemek, IL;
David Zfira, Migdal Haemek, IL;
Tower Semiconductor Ltd., Migdal Haemek, IL;
Abstract
A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.