The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2010

Filed:

Dec. 30, 2008
Applicants:

Hae-jung Lee, Gyeonggi-do, KR;

Jae-seon Yu, Gyeonggi-do, KR;

Jae-kyun Lee, Gyeonggi-do, KR;

Sang-rok OH, Gyeonggi-do, KR;

Inventors:

Hae-Jung Lee, Gyeonggi-do, KR;

Jae-Seon Yu, Gyeonggi-do, KR;

Jae-Kyun Lee, Gyeonggi-do, KR;

Sang-Rok Oh, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor, Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.


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