The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2010
Filed:
Sep. 14, 2007
Sang-jin Park, Yongin-si, KR;
In-jun Hwang, Yongin-si, KR;
Jae-woong Hyun, Uijeongbu-si, KR;
Yoon-dong Park, Yongin-si, KR;
Kwang-soo Seol, Suwon-si, KR;
Sang-min Shin, Seoul, KR;
Sang-moo Choi, Yongin-si, KR;
Ju-hee Park, Yongin-si, KR;
Sang-jin Park, Yongin-si, KR;
In-jun Hwang, Yongin-si, KR;
Jae-woong Hyun, Uijeongbu-si, KR;
Yoon-dong Park, Yongin-si, KR;
Kwang-soo Seol, Suwon-si, KR;
Sang-min Shin, Seoul, KR;
Sang-moo Choi, Yongin-si, KR;
Ju-hee Park, Yongin-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the storage node layer and the control gate electrode, and first and second channel regions surrounding the control gate electrode and separated by a pair of opposing separating insulating layers. A method of operating the semiconductor memory device may include programming data in the storage node layer by charge tunneling through the blocking insulating layer, thus achieving relatively high reliability and efficiency.