The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2010
Filed:
Feb. 28, 2008
Seung-won Lim, Bucheon-si, KR;
O-seob Jeon, Seoul, KR;
Joon-seo Son, Seoul, KR;
Keun-hyuk Lee, Bucheon-si, KR;
Yun-hwa Choi, Incheon, KR;
Seung-won Lim, Bucheon-si, KR;
O-Seob Jeon, Seoul, KR;
Joon-seo Son, Seoul, KR;
Keun-hyuk Lee, Bucheon-si, KR;
Yun-hwa Choi, Incheon, KR;
Fairchild Korea Semiconductor Ltd., Bucheon-si, Gyeonggi-do, KR;
Abstract
Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.