The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2010

Filed:

Dec. 07, 2007
Applicant:

Tetsuya Taguwa, Tokyo, JP;

Inventor:

Tetsuya Taguwa, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes an N-channel transistor having an N-type gate electrode and a P-channel transistor having a P-type gate electrode which are formed on a semiconductor substrate. The P-type gate electrode includes a first silicon layer formed as the lowest layer, and doped with a P-type impurity; a second silicon layer formed on the first silicon layer; and a metal containing layer formed on the second silicon layer. The N-type gate electrode includes a third silicon layer formed as the lowest layer and doped with an N-type impurity; a fourth silicon layer formed on the third silicon layer; and a metal containing layer formed on the fourth silicon layer. At least one of the second silicon layer and the fourth silicon layer is doped with no impurity or an impurity of a conductive type opposite to that of the impurity in a corresponding one of the first silicon layer and third silicon layer.


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