The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Mar. 13, 2007
Yan Wang, Campbell, CA (US);
Nui Chong, Cupertino, CA (US);
Hong-tsz Pan, Cupertino, CA (US);
Bang-thu Nguyen, Santa Clara, CA (US);
Jonathan Jung-ching Ho, Fremont, CA (US);
Qi Lin, Cupertino, CA (US);
Yuhao Luo, San Jose, CA (US);
Hing Yee Angela Wong, San Jose, CA (US);
Xin X. Wu, Fremont, CA (US);
Yuezhen Fan, San Jose, CA (US);
Yan Wang, Campbell, CA (US);
Nui Chong, Cupertino, CA (US);
Hong-Tsz Pan, Cupertino, CA (US);
Bang-Thu Nguyen, Santa Clara, CA (US);
Jonathan Jung-Ching Ho, Fremont, CA (US);
Qi Lin, Cupertino, CA (US);
Yuhao Luo, San Jose, CA (US);
Hing Yee Angela Wong, San Jose, CA (US);
Xin X. Wu, Fremont, CA (US);
Yuezhen Fan, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.