The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2010

Filed:

Nov. 18, 2005
Applicants:

Dong-suk Shin, Suwon-si, KR;

Ueno Tetsuji, Suwon-si, KR;

Seung-hwan Lee, Suwon-si, KR;

Ho Lee, ChunAnn, KR;

Hwa-sung Rhee, SungNam, KR;

Inventors:

Dong-Suk Shin, Suwon-si, KR;

Ueno Tetsuji, Suwon-si, KR;

Seung-Hwan Lee, Suwon-si, KR;

Ho Lee, ChunAnn, KR;

Hwa-Sung Rhee, SungNam, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/148 (2006.01); H01L 27/01 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.


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