The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Mar. 17, 2006
Koji Otsuka, Niiza, JP;
Tetsuji Moku, Niiza, JP;
Junji Sato, Niiza, JP;
Yoshiki Tada, Niiza, JP;
Takashi Yoshida, Niiza, JP;
Koji Otsuka, Niiza, JP;
Tetsuji Moku, Niiza, JP;
Junji Sato, Niiza, JP;
Yoshiki Tada, Niiza, JP;
Takashi Yoshida, Niiza, JP;
Sanken Electric Co., Ltd., , JP;
Abstract
A light-emitting diode is built on a silicon substrate which has been doped with a p-type impurity to possess sufficient conductivity to provide part of the current path through the LED. The p-type silicon substrate has epitaxially grown thereon a buffer region of n-type AlInGaN. Further grown epitaxially on the buffer region is the main semiconductor region of the LED which comprises a lower confining layer of n-type GaN, an active layer for generating light, and an upper confining layer of p-type GaN. In the course of the growth of the buffer region and main semiconductor region there occurs a thermal diffusion of gallium and other Group III elements from the buffer region into the p-type silicon substrate, with the consequent creation of a p-type low-resistance region in the substrate. Interface levels are created across the heterojunction between p-type silicon substrate and n-type buffer region. The interface levels expedite carrier transport from substrate to buffer region, contributing to reduction of the drive voltage requirement of the LED.