The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Dec. 10, 2007
Tibor Bolom, Fishkill, NY (US);
Kaushik Chanda, Fishkill, NY (US);
Ronald G. Filippi, Wappingers Falls, NY (US);
Stephan Grunow, Wappingers Falls, NY (US);
Paul S. Mclaughlin, Poughkeepsie, NY (US);
Sujatha Sankaran, New Paltz, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Theodorus E. Standaert, Pine Bush, NY (US);
James Werking, Hopewell Junction, NY (US);
Tibor Bolom, Fishkill, NY (US);
Kaushik Chanda, Fishkill, NY (US);
Ronald G. Filippi, Wappingers Falls, NY (US);
Stephan Grunow, Wappingers Falls, NY (US);
Paul S. McLaughlin, Poughkeepsie, NY (US);
Sujatha Sankaran, New Paltz, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Theodorus E. Standaert, Pine Bush, NY (US);
James Werking, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Advanced Micro Devices, Inc. (AMD), Sunnyvale, CA (US);
Abstract
A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.