Method and structure for fabricating capacitor devices for integrated circuits

Abstract

A dynamic random access memory device including a capacitor structure, e.g., trench, stack. The device includes a substrate (e.g., silicon, silicon on insulator, epitaxial silicon) having a surface region. The device includes an interlayer dielectric region overlying the surface region. In a preferred embodiment, the interlayer dielectric region has an upper surface and a lower surface. The device has a container structure within a portion of the interlayer dielectric region. The container structure extends from the upper surface to the lower surface. The container structure has a first width at the upper surface and a second width at the lower surface. The container structure has an inner region extending from the upper surface to the lower surface. In a specific embodiment, the container structure has a higher dopant concentration within a portion of the inner region within a vicinity of the lower surface and on a portion of the inner region near the vicinity of the lower surface. The device also has a doped polysilicon layer overlying the inner region of the trench structure. The device has a first hemispherical grained silicon material having a first grain dimension near the vicinity of the lower surface and a second hemispherical grained silicon material having a second grain dimension near a vicinity of the upper surface of the container structure. In a preferred embodiment, the first grain dimension has an average size of no greater than about ½ of an average size of the second grain dimension to prevent any bridging of any portions of the hemispherical grained silicon material within the vicinity of the lower surface.