The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
May. 16, 2008
Jing LI Yuan, Gyunggi-do, KR;
Jae Cheon Doh, Gyunggi-do, KR;
Tae Hoon Kim, Gyunggi-do, KR;
SI Joong Yang, Gyunggi-do, JP;
Seung Wook Park, Seoul, KR;
Jing Li Yuan, Gyunggi-do, KR;
Jae Cheon Doh, Gyunggi-do, KR;
Tae Hoon Kim, Gyunggi-do, KR;
Si Joong Yang, Gyunggi-do, JP;
Seung Wook Park, Seoul, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line.