The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7670877 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 02, 2010

Filed:

Oct. 16, 2007
Applicants:

William E. Murphy, Vestal, NY (US);

Ryan S. Riegle, Endicott, NY (US);

Richard W. Shields, Endwell, NY (US);

David L. Vos, Apalachin, NY (US);

Inventors:

William E. Murphy, Vestal, NY (US);

Ryan S. Riegle, Endicott, NY (US);

Richard W. Shields, Endwell, NY (US);

David L. Vos, Apalachin, NY (US);

Assignee:

Lockheed Martin Corporation, Bethesda, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of packaging a semiconductor component with a printed wiring board is disclosed. The method includes determining a first distance, applying a thin film onto a surface of the semiconductor component such that the thin film is spaced apart from a support of the semiconductor, applying a solder pad onto the printed wiring board, placing the semiconductor component with the thin film onto the printed wiring board, and positioning the thin film adjacent the solder pad.


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Murphy, William. (2010). Reliability enhancement process (U.S. Patent No. 7670877). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7670877

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