The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2010
Filed:
Sep. 30, 2003
Dennis Kim, San Francisco, CA (US);
Jason Wei, Cupertino, CA (US);
Yohan Frans, Palo Alto, CA (US);
Todd Bystrom, Los Altos, CA (US);
Nhat Nguyen, San Jose, CA (US);
Kevin Donnelly, Los Altos, CA (US);
Dennis Kim, San Francisco, CA (US);
Jason Wei, Cupertino, CA (US);
Yohan Frans, Palo Alto, CA (US);
Todd Bystrom, Los Altos, CA (US);
Nhat Nguyen, San Jose, CA (US);
Kevin Donnelly, Los Altos, CA (US);
Rambus Inc., Los Altos, CA (US);
Abstract
A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.