The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2010

Filed:

Nov. 15, 2006
Applicants:

Robert Wieland, Munich, DE;

Dieter Bollmann, Munich, DE;

Inventors:

Robert Wieland, Munich, DE;

Dieter Bollmann, Munich, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/673 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a bipolar carrier wafer and a mobile, bipolar electrostatic wafer arrangement. Carrier wafers and wafer arrangements of this type can be used in particular in the field of handling technology of semiconductor wafers. The carrier wafer according to the invention serves for mounting a disc-shaped semiconductor component. It has a first surface () as front-side and a second surface () which is situated opposite the first surface () as rear-side. The carrier wafer is configured such that it has a carrier layer (), an electrically insulating cover layer () which surrounds the carrier layer and an electrically conductive layer (), the latter being disposed on the electrically insulating cover layer and being structured in at least two regions which are separated from each other electrically as electrodes. Electrical contacts are disposed on the rear-side () of the carrier wafer, these electrical contacts being connected to the two electrodes disposed on the front-side (). On the electrically conductive layer (), in addition an electrically insulating cover layer () is disposed which covers both the front-side () and the edge of the carrier wafer between the front-side () and the rear-side ().


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