The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Nov. 07, 2008
Hieu Van Tran, San Jose, CA (US);
Hung Quoc Nguyen, Fremont, CA (US);
Anh Ly, San Jose, CA (US);
Sheng-hsiung Hsueh, San Jose, CA (US);
Sang Thanh Nguyen, Union City, CA (US);
Loc B. Hoang, San Jose, CA (US);
Steve Choi, Irvine, CA (US);
Thuan T. VU, San Jose, CA (US);
Hieu Van Tran, San Jose, CA (US);
Hung Quoc Nguyen, Fremont, CA (US);
Anh Ly, San Jose, CA (US);
Sheng-Hsiung Hsueh, San Jose, CA (US);
Sang Thanh Nguyen, Union City, CA (US);
Loc B. Hoang, San Jose, CA (US);
Steve Choi, Irvine, CA (US);
Thuan T. Vu, San Jose, CA (US);
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Abstract
Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.