The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Sep. 04, 2008
Hyung Jin Jeon, Gunpo-si, KR;
Sung Yi, Suwon-si, KR;
Jong Yun Lee, Incheon-si, KR;
Young DO Kweon, Seoul, KR;
Jong Hwan Baek, Seoul, KR;
Hyung Jin Jeon, Gunpo-si, KR;
Sung Yi, Suwon-si, KR;
Jong Yun Lee, Incheon-si, KR;
Young Do Kweon, Seoul, KR;
Jong Hwan Baek, Seoul, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.