The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7661081 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 09, 2010

Filed:

Apr. 11, 2008
Applicants:

Robert J. Allen, Jericho, VT (US);

Daria R. Dooling, Huntington, VT (US);

Jason D. Hibbeler, Williston, VT (US);

Daniel N. Maynard, Craftsbury Common, VT (US);

Sarah C. Prue, Richmond, VT (US);

Ralph J. Williams, Essex Junction, VT (US);

Inventors:

Robert J. Allen, Jericho, VT (US);

Daria R. Dooling, Huntington, VT (US);

Jason D. Hibbeler, Williston, VT (US);

Daniel N. Maynard, Craftsbury Common, VT (US);

Sarah C. Prue, Richmond, VT (US);

Ralph J. Williams, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.


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