The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2010

Filed:

Feb. 29, 2008
Applicants:

Dieter Kohlert, Pentling, DE;

Erhard Sixt, Mainburg, DE;

Rainer Holmer, Steinach, DE;

Georg Seidemann, Landshut, DE;

Berthold Schuderer, Regensburg, DE;

Gunther Mackh, Neumarkt, DE;

Sabine Penka, Unterhaching, DE;

Grit Schwalbe-dietrich, Dresden, DE;

Bernhard Duschinger, Teublitz, DE;

Josef Hermann, Regensburg, DE;

Inventors:

Dieter Kohlert, Pentling, DE;

Erhard Sixt, Mainburg, DE;

Rainer Holmer, Steinach, DE;

Georg Seidemann, Landshut, DE;

Berthold Schuderer, Regensburg, DE;

Gunther Mackh, Neumarkt, DE;

Sabine Penka, Unterhaching, DE;

Grit Schwalbe-Dietrich, Dresden, DE;

Bernhard Duschinger, Teublitz, DE;

Josef Hermann, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.


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