The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2010

Filed:

Feb. 21, 2006
Applicants:

Toan Thanh Nguyen, San Jose, CA (US);

Thungoc Tran, San Jose, CA (US);

Sergey Yuryevich Shumarayev, San Leandro, CA (US);

Arch Zaliznyak, San Jose, CA (US);

Tim Tri Hoang, San Jose, CA (US);

Ramanand Venkata, San Francisco, CA (US);

Chong Lee, San Ramon, CA (US);

Inventors:

Toan Thanh Nguyen, San Jose, CA (US);

Thungoc Tran, San Jose, CA (US);

Sergey Yuryevich Shumarayev, San Leandro, CA (US);

Arch Zaliznyak, San Jose, CA (US);

Tim Tri Hoang, San Jose, CA (US);

Ramanand Venkata, San Francisco, CA (US);

Chong Lee, San Ramon, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device ('PLD') or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).


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