The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2010
Filed:
Apr. 07, 2006
Applicants:
Yuji Watanabe, Tokyo, JP;
Koji Hosokawa, Tokyo, JP;
Hisashi Tanie, Ibaraki, JP;
Inventors:
Assignee:
Elpida Memory, Inc., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/488 (2006.01); H01L 23/48 (2006.01); H01L 25/07 (2006.01); H01L 23/12 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
Abstract
An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (), no ordinary wiring line is formed in a region ((A)) in the vicinity of the support ball () and a region ((B)) at the end of the semiconductor chip facing the support ball (), which are the stress concentration regions of the package substrate (). Instead, a wiring line ((C)) is formed away from these regions or a wide wiring line is formed in these regions.