The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2010

Filed:

May. 09, 2007
Applicants:

Yee-chia Yeo, Albany, CA (US);

Chun-chieh Lin, Hsin-Chu, TW;

Fu-liang Yang, Hsin-Chu, TW;

Chen Ming HU, Hsin-Chu, TW;

Inventors:

Yee-Chia Yeo, Albany, CA (US);

Chun-Chieh Lin, Hsin-Chu, TW;

Fu-Liang Yang, Hsin-Chu, TW;

Chen Ming Hu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.


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