The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Aug. 01, 2003
Hong Wang, San Jose, CA (US);
Tor Aamodt, Santa Clara, CA (US);
Per Hammarlund, Hillsboro, OR (US);
John Shen, San Jose, CA (US);
Xinmin Tian, San Jose, CA (US);
Milind Girkar, Sunnyvale, CA (US);
Perry Wang, San Jose, CA (US);
Steve Shih-wei Liao, San Jose, CA (US);
Hong Wang, San Jose, CA (US);
Tor Aamodt, Santa Clara, CA (US);
Per Hammarlund, Hillsboro, OR (US);
John Shen, San Jose, CA (US);
Xinmin Tian, San Jose, CA (US);
Milind Girkar, Sunnyvale, CA (US);
Perry Wang, San Jose, CA (US);
Steve Shih-wei Liao, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is permitted to execute Store instructions. Store blocker logic operates to prevent data associated with a Store instruction in a helper thread from being committed to memory. Dependence blocker logic operates to prevent data associated with a Store instruction in a speculative helper thread from being bypassed to a Load instruction in a non-speculative thread.