The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2010

Filed:

Aug. 18, 2006
Applicants:

Matthias Knoth, San Jose, CA (US);

Ryan C. Kinter, Sammamish, WA (US);

Inventors:

Matthias Knoth, San Jose, CA (US);

Ryan C. Kinter, Sammamish, WA (US);

Assignee:

MIPS Technologies, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way selection data bits associated with cache accesses. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal activates only the cache dataram that stores the needed data.


Find Patent Forward Citations

Knoth, Matthias. (2010). Methods for reducing data cache access power in a processor using way selection bits (U.S. Patent No. 7657708). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7657708

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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