The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Dec. 31, 2007
Applicants:
Sapumal Wijeratne, Portland, OR (US);
Matthew W. Ernest, Hillsboro, OR (US);
Brian A. Kuns, Beaverton, OR (US);
Inventors:
Sapumal Wijeratne, Portland, OR (US);
Matthew W. Ernest, Hillsboro, OR (US);
Brian A. Kuns, Beaverton, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01);
U.S. Cl.
CPC ...
Abstract
Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.
Wijeratne, Sapumal. (2010). Ultra low voltage, low leakage, high density, variation tolerant memory bit cells (U.S. Patent No. 7656702). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7656702
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile