The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2010

Filed:

Dec. 15, 2005
Applicants:

Yosuke Kawamata, Tokyo, JP;

Makoto Kitayama, Tokyo, JP;

Inventors:

Yosuke Kawamata, Tokyo, JP;

Makoto Kitayama, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01H 37/76 (2006.01); H01H 85/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are a semiconductor device capable of reducing the number of program fuses used therein, and a fuse circuit selection method capable of reducing the number of program fuses. The semiconductor device includes: a fuse circuit () and an entire inversion fuse circuit (), each of which includes plural program fuses, and which store desired addresses based on cutting patterns of the plural program fuses, wherein the fuse circuit () and the entire inversion fuse circuit () are configured to be capable of storing addresses different from each other based on the same cutting pattern. As described above, since plural types of the cutting patterns of the program fuses exist even in the same address, the fuse circuit for use is appropriately selected, thus it is made possible to reduce the number of fuse elements to be cut as a whole. Thus, manufacturing cost of the semiconductor device can be reduced, and in addition, it is made possible to enhance reliability of the semiconductor device.


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