The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Jun. 12, 2007
Chien-liang Chen, Hsin-Chu, TW;
Wen-chih Yang, Hsin-Chu, TW;
Chii-horng LI, Jhu-Bei, TW;
Harry Chuang, Austin, TX (US);
Chien-Liang Chen, Hsin-Chu, TW;
Wen-Chih Yang, Hsin-Chu, TW;
Chii-Horng Li, Jhu-Bei, TW;
Harry Chuang, Austin, TX (US);
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as a discontinuous layer. This may be done, for example, by depositing an appropriate CESL, then forming an ILD layer, and simultaneously reducing the ILD layer and the CESL to a desired level. The discontinuity preferably exposes the gate electrode, or the metal contact region formed on it, if present. The upper boundary of the CESL may be further reduced, however, to position it below the upper boundary of the gate electrode.