The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Jul. 23, 2008
Mei-ling Chao, Hsinchu, TW;
Chia-yun Chen, Tainan, TW;
Tai-hsiang Lai, Miaoli County, TW;
Tien-hao Tang, Hsinchu, TW;
Mei-Ling Chao, Hsinchu, TW;
Chia-Yun Chen, Tainan, TW;
Tai-Hsiang Lai, Miaoli County, TW;
Tien-Hao Tang, Hsinchu, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region.