The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2010

Filed:

Apr. 01, 2005
Applicants:

Chi-ming Tsai, Sunnyvale, CA (US);

Lai-chee Man, Sunnyvale, CA (US);

Yao-ting Wang, Sunnyvale, CA (US);

Fang-cheng Chang, Sunnyvale, CA (US);

Inventors:

Chi-Ming Tsai, Sunnyvale, CA (US);

Lai-Chee Man, Sunnyvale, CA (US);

Yao-Ting Wang, Sunnyvale, CA (US);

Fang-Cheng Chang, Sunnyvale, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
Abstract

A Wafer Image Modeling and Prediction System ('WIMAPS') is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques ('RET') and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process so as to allow designers to filter predict printed silicon contours prior to application of RET and printing processes to the circuit design.


Find Patent Forward Citations

Tsai, Chi-Ming. (2010). Modeling resolution enhancement processes in integrated circuit fabrication (U.S. Patent No. 7653890). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7653890

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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