The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2010
Filed:
Dec. 21, 2006
Osamu Ozawa, Tokyo, JP;
Toshio Sasaki, Tokyo, JP;
Ryo Mori, Tokyo, JP;
Takashi Kuraishi, Tokyo, JP;
Yoshihiko Yasu, Tokyo, JP;
Koichiro Ishibashi, Tokyo, JP;
Osamu Ozawa, Tokyo, JP;
Toshio Sasaki, Tokyo, JP;
Ryo Mori, Tokyo, JP;
Takashi Kuraishi, Tokyo, JP;
Yoshihiko Yasu, Tokyo, JP;
Koichiro Ishibashi, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit () and a power-supply-uninterrupted circuit (). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch () between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.