Complementary field-effect transistors having enhanced performance with a single capping layer

Abstract

Performance of a complementary metal-oxide-semiconductor (CMOS) device having n-channel MOS transistors and p-channel MOS transistors is enhanced by providing a single capping layer overlying the MOS transistors with the single capping layer inducing stress in the transistor channel regions to enhance carrier mobility. The n-channel transistor is preferably fabricated in silicon having a (100) crystalline channel surface orientation, and the p-channel transistor is preferably fabricated in silicon having a (110) channel surface crystalline orientation. A tensile stress in the single capping layer induces tensile stress in the channel of the (100) n-channel transistor thereby enhancing the mobility of electrons while tensile stress in the single capping layer induces compressive stress in the channel of the (110) p-channel transistor thereby enhancing the mobility of holes. Alternatively, the n-channel transistor is fabricated in silicon having a (110) crystalline channel surface orientation, and the p-channel transistor is fabricated in silicon having a (100) channel surface crystalline orientation. A compressive stress in the single capping layer induces tensile stress in the channel of the (110) n-channel transistor thereby enhancing the mobility of electrons while compressive stress in the single capping layer induces compressive stress in the channel of the (100) p-channel transistor thereby enhancing the mobility of holes.