The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2010

Filed:

Jan. 07, 2008
Applicant:

Chih-chuan Lin, San Jose, CA (US);

Inventor:

Chih-Chuan Lin, San Jose, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques are described to monitor charging of an integrated circuit during manufacturing processes. In one example, an integrated circuit includes first and second pads adapted to be charged by charge carriers during manufacture of the integrated circuit. The integrated circuit also includes a reference nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate is coupled to the first pad. The integrated circuit further includes a charging protection device coupled to the control gate of the reference memory cell and adapted to limit the gate voltage of the control gate induced by the charge carriers. In addition, the integrated circuit includes a charging monitor nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate is coupled to the second pad but not to a charging protection device adapted to limit the gate voltage of the control gate.


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