The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2010

Filed:

May. 15, 2006
Applicants:

Manish Pandey, Saratoga, CA (US);

Samuel L. Kerner, Dorchester, MA (US);

Chih-chang Lin, Saratoga, CA (US);

Inventors:

Manish Pandey, Saratoga, CA (US);

Samuel L. Kerner, Dorchester, MA (US);

Chih-chang Lin, Saratoga, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method for analyzing a circuit composed of MOS devices. The method can be used to direct MOS devices in static and dynamic circuits and involves identifying an undirected MOS device that connects nets. Functions of the nets that cause each net to be logic values are defined as a function of inputs to the circuit. The defined functions can include pulldown functions or both pullup and pulldown functions. A set of rules is used to determine the direction of a signal that flows through a device and applies defined functions. The rules for analyzing static devices may differ from the rules for analyzing dynamic devices. Devices that are determined to have uni-directional signal flow can be directed. Additionally, devices having bi-directional signal flow and uni-directional observability can be directed.


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