The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7642633 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 05, 2010

Filed:

Feb. 06, 2006
Applicants:

Tetsuya Hirose, Nagano, JP;

Naoyuki Shinonaga, Nagano, JP;

Shuichi Osaka, Nagano, JP;

Inventors:

Tetsuya Hirose, Nagano, JP;

Naoyuki Shinonaga, Nagano, JP;

Shuichi Osaka, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes. Then, the capsule type semiconductor package and the logic chip are laminated on the main substrate, and desired connections are provided between the electrodes on the rear surface of the interposer substrate of the capsule type semiconductor package, the electrodes of the logic chip and the electrodes on the front surface of the main substrate. The capsule type semiconductor package and the logic chip are sealed to the front surface of the main substrate by a resin to obtain a system-in-package type semiconductor device.


Find Patent Forward Citations

Hirose, Tetsuya. (2010). Semiconductor device including capsule type semiconductor package and semiconductor chip in stacking manner (U.S. Patent No. 7642633). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7642633

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