The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2010
Filed:
Jan. 26, 2007
Yong-suk Choi, Jiwaseong-si, KR;
Jeong-uk Han, Suwon-si, KR;
Hee-seog Jeon, Suwon-si, KR;
Yong-tae Kim, Yongin-si, KR;
Seung-jin Yang, Seoul, KR;
Hyok-ki Kwon, Yongin-si, KR;
Yong-Suk Choi, Jiwaseong-si, KR;
Jeong-Uk Han, Suwon-si, KR;
Hee-Seog Jeon, Suwon-si, KR;
Yong-Tae Kim, Yongin-si, KR;
Seung-Jin Yang, Seoul, KR;
Hyok-Ki Kwon, Yongin-si, KR;
Abstract
a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.