The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2009

Filed:

Dec. 27, 2007
Applicants:

Jong-ho Yun, Suwon-si, KR;

Gil-heyun Choi, Seoul, KR;

Byung-hee Kim, Seoul, KR;

Hyun-su Kim, Suwon-si, KR;

Eun-ok Lee, Hwaseong-si, KR;

Inventors:

Jong-Ho Yun, Suwon-si, KR;

Gil-Heyun Choi, Seoul, KR;

Byung-Hee Kim, Seoul, KR;

Hyun-Su Kim, Suwon-si, KR;

Eun-Ok Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.


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